1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an insulated gate bipolar transistor.
2. Description of the Related Art
Insulated gate bipolar transistors (IGBTs) are conventionally used for power semiconductor devices. It is a well-known structure wherein an IGBT has trenches filled with gate electrodes on a surface of a substrate.
FIG. 16 is a plane view showing a conventional IGBT structure wherein trenches filled with gate electrodes are provided on the surface of the substrate disclosed in Japanese Laid-Open Patent Application No. H08-316479. FIG. 17 is a cross-sectional view showing the cross-sectional structure at the line X-X in FIG. 16. FIG. 18 is a cross-sectional view showing the cross-sectional structure at the line Y-Y in FIG. 16. FIGS. 16 to 18 are schematic views and the components are not shown in their actual scale ratios.
As shown in FIGS. 17 and 18, a conventional IGBT has an N− layer 106 consisting of a low concentration N-type impurity region formed on a collector layer 112 consisting of a high concentration P-type impurity region via a buffer layer 111 consisting of a high concentration N-type impurity region. A well layer 105 consisting of an N-type impurity region is formed in the surface part of the N− layer 106. A body layer 102 consisting of a P-type impurity region is formed in the surface part of the well layer 105. Multiple trenches 121 are formed through the body layer 102, reaching the well layer 105. Each trench 121 is filled with a gate electrode 108 made of, for example, polysilicon and the like via a gate insulating film 107 formed on the inner surface of the trench 121. As shown in FIGS. 16 to 18, each gate electrode 108 (trench 121) is continuously formed in a specific direction. A collector electrode 113 is provided on the underside of the collector layer 112.
As shown in FIGS. 16 and 17, emitter layers 104 each consisting of a high concentration N-type impurity region is formed where the main surface of the body layer 102 and trenches 121 meet along the trenches 121. Contact layers 101 each consisting of a high concentration P-type impurity region are formed between the emitter layers 104 in the adjacent trenches 121 along the trenches 121. An emitter electrode 114 is provided on the top surfaces of the emitter layers 104 and contact layers 101 and electrically connected both to the emitter layers 104 and to the contact layers 101. Oxide films 109 are interposed between each gate electrode 108 and emitter electrode 114 so that the gate electrode 108 and emitter electrode 114 are electrically insulated. As shown in FIGS. 16 and 18, the gate electrodes 108 are electrically connected to each other via coupling electrodes 115.
On the other hand, as shown in FIGS. 16 to 18, when the IGBT must have high breakdown voltage, a plurality of floating ring layers 103 (103a, 103b, 103c) each consisting of a high concentration P-type impurity region is provided around the body layer 102 in which multiple trenches 121 are formed, being spaced apart from the body layer 102. A channel stopper layer 101 consisting of a high concentration N-type impurity region is provided around the outermost floating ring layer 103c, being spaced apart therefrom.
In the IGBT having the above-described structure, the N-type emitter layer 104, P-type body layer 102 and N-type well layer 105, which are formed along the each trench 121, constitute an N-channel type MOS transistor (see FIG. 17). On the other hand, the P-type contact layer 101, P-type body layer 102, N-type well layer 105, N− layer 106, N-type buffer layer 111, and P-type collector layer 112 constitute a PNP bipolar transistor (see FIG. 17). The IGBT is operated by combined operations of the MOS and the PNP transistors.
For example, in a state that negative potential is applied to the emitter electrode 114 and concurrently positive potential is applied to the collector electrode 113, a positive potential which is larger than that of being applied to the emitter electrode 114, is applied to the each gate electrode 108. In such a case, an inversion layer is formed on the surface of the P-type body layer 102 that is in contact with the gate insulating film 107. Thus, the MOS transistor turns on-state and electron current flows through the MOS transistor. The electron current has a function as base current for the PNP transistor. Namely, when the electron current flows, the PNP transistor turns on-state and hole current flows through the collector electrode 113 and emitter electrode 114.
As described above, in the IGBT, when electron current flows in the MOS transistor, the base current is provided to the PNP transistor and the PNP transistor turns on-state. Therefore, in the IGBT, on-state and off-state of the PNP transistor is switched by switching on-state and off-state of the each MOS transistor by controlling a voltage applied to the each gate electrode 108.
With the above described structure, the well layer 105 forms a potential barrier against holes in the direction from the N− layer 106 to the body layer 102. Namely, the density of holes moving from the collector layer 112 to the body layer 102 in the on-state is increased in the well layer 105, reducing an on-resistance of the IGBT. Therefore, with the provision of the well layer 105, the on-resistance can be lowered for the IGBT having the same chipsize. In other words, with the provision of the well layer 105, the chip can be downsized for the IGBT having the same on-resistance. The well layer 105 can further reduce the on-resistance when it increases the hole density in a larger area, and a well layer 105 is formed to completely surround the entire body layer 102 in the plane view as shown in FIG. 16.